US 11,869,957 B2
Compound semiconductor device
Kenji Sasaki, Nagaokakyo (JP); Kingo Kurotani, Nagaokakyo (JP); Takashi Kitahara, Nagaokakyo (JP); and Shigeki Koya, Nagaokakyo (JP)
Assigned to Murata Manufacturing Co., Ltd., Kyoto-fu (JP)
Filed by Murata Manufacturing Co., Ltd., Kyoto-fu (JP)
Filed on Aug. 10, 2021, as Appl. No. 17/398,909.
Application 17/398,909 is a continuation of application No. 17/097,937, filed on Nov. 13, 2020, granted, now 11,508,834.
Application 17/097,937 is a continuation in part of application No. 16/568,154, filed on Sep. 11, 2019, granted, now 10,868,155, issued on Dec. 15, 2020.
Application 16/568,154 is a continuation in part of application No. 16/355,172, filed on Mar. 15, 2019, granted, now 10,714,602, issued on Jul. 14, 2020.
Application 16/355,172 is a continuation of application No. 15/709,017, filed on Sep. 19, 2017, granted, now 10,276,701, issued on Apr. 30, 2019.
Application 15/709,017 is a continuation of application No. 14/932,497, filed on Nov. 4, 2015, granted, now 9,825,156, issued on Nov. 21, 2017.
Claims priority of application No. 2014-240327 (JP), filed on Nov. 27, 2014.
Prior Publication US 2021/0367066 A1, Nov. 25, 2021
Int. Cl. H01L 29/737 (2006.01); H01L 23/00 (2006.01); H01L 23/482 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 23/535 (2006.01); H01L 27/082 (2006.01); H01L 29/40 (2006.01); H03F 3/19 (2006.01)
CPC H01L 29/7371 (2013.01) [H01L 23/4824 (2013.01); H01L 23/535 (2013.01); H01L 24/13 (2013.01); H01L 27/0823 (2013.01); H01L 29/0692 (2013.01); H01L 29/40 (2013.01); H01L 29/41708 (2013.01); H03F 3/19 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/1302 (2013.01); H01L 2224/13013 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/13051 (2013.01); H03F 2200/408 (2013.01); H03F 2200/451 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a heterojunction bipolar transistor including a plurality of unit transistors;
a plurality of capacitors, each capacitor being electrically connected between an RF input wire and a base wire for each unit transistor of the plurality of unit transistors; and
an emitter wire electrically connected to emitters of the plurality of unit transistors,
wherein
the plurality of unit transistors are arranged in a first direction,
the emitter wire is disposed above the emitters of the plurality of unit transistors,
the plurality of unit transistors include at least one first unit transistor and at least one second unit transistor,
the emitter of the first unit transistor being disposed in the first direction,
the emitter of the second unit transistor being disposed in the first direction,
the emitter of the first unit transistor and the emitter of the second unit transistor are provided in a staggered arrangement,
each of the capacitors is not covered by the emitter wire,
a length of the base wire connected to the first unit transistor is different from a length of the base wire connected to the second unit transistor, and
a distance of the capacitor for the first unit transistor to the emitter of the first unit transistor is less than a distance of the capacitor for the second unit transistor to the emitter of the second unit transistor.