US 11,869,933 B2
Device isolator with reduced parasitic capacitance
Raja Selvaraj, Bangalore (IN); Anant Shankar Kamath, Plano, TX (US); Byron Lovell Williams, Plano, TX (US); Thomas D. Bonifield, Dallas, TX (US); and John Kenneth Arch, Richardson, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Aug. 10, 2021, as Appl. No. 17/398,292.
Application 17/398,292 is a division of application No. 16/228,817, filed on Dec. 21, 2018, granted, now 11,107,883.
Application 15/714,682 is a division of application No. 14/680,211, filed on Apr. 7, 2015, granted, now 9,806,148, issued on Oct. 31, 2017.
Application 16/228,817 is a continuation of application No. 15/714,682, filed on Sep. 25, 2017, granted, now 10,186,576, issued on Jan. 22, 2019.
Prior Publication US 2021/0367030 A1, Nov. 25, 2021
Int. Cl. H01L 29/06 (2006.01); H01L 27/06 (2006.01); H01L 21/761 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 49/02 (2006.01); H01L 21/265 (2006.01)
CPC H01L 29/0646 (2013.01) [H01L 21/265 (2013.01); H01L 21/761 (2013.01); H01L 23/5223 (2013.01); H01L 23/5227 (2013.01); H01L 23/5286 (2013.01); H01L 24/05 (2013.01); H01L 27/0676 (2013.01); H01L 28/10 (2013.01); H01L 28/20 (2013.01); H01L 28/40 (2013.01); H01L 28/60 (2013.01); H01L 2224/48463 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit, comprising:
forming a first terminal over a semiconductor substrate having a first conductivity type;
forming a second terminal between the first terminal and a surface of the semiconductor substrate, the first terminal being separated from the second terminal by a dielectric layer;
forming a first p-n junction between the semiconductor substrate and the second terminal, the first p-n junction having a first orientation with respect to the substrate surface;
forming a second p-n junction between the first p-n junction and the second terminal, the second p-n junction having a second opposite orientation with respect to the substrate surface; and
forming a third p-n junction between the second p-n junction and the second terminal, the third p-n junction have the first orientation.