US 11,869,836 B2
Method for forming a semiconductor device
Donghee Seo, Suwon-si (KR); Heonbok Lee, Suwon-si (KR); Tae-Yeol Kim, Hwaseong-si (KR); Daeyong Kim, Yongin-si (KR); and Dohyun Lee, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 6, 2023, as Appl. No. 18/105,955.
Application 18/105,955 is a continuation of application No. 17/503,723, filed on Oct. 18, 2021, granted, now 11,581,253.
Application 17/503,723 is a continuation of application No. 16/893,540, filed on Jun. 5, 2020, granted, now 11,152,297, issued on Oct. 19, 2021.
Claims priority of application No. 10-2019-0155625 (KR), filed on Nov. 28, 2019.
Prior Publication US 2023/0187335 A1, Jun. 15, 2023
Int. Cl. H01L 23/49 (2006.01); H01L 29/78 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/49844 (2013.01) [H01L 23/49811 (2013.01); H01L 29/78 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device, the method comprising:
forming an interlayer insulating layer on a substrate;
forming a contact hole penetrating the interlayer insulating layer;
forming a lower pattern and a barrier pattern in the contact hole such that the barrier pattern is between the lower pattern and the interlayer insulating layer;
forming an upper insulating layer on the interlayer insulating layer such that the upper insulating layer covers topmost surfaces of the lower pattern and the barrier pattern;
forming a trench in the upper insulating layer such that the trench exposes the topmost surfaces of the lower pattern and the barrier pattern;
forming a recess region in the interlayer insulating layer by recessing the topmost surfaces of the lower pattern and the barrier pattern; and
forming an upper pattern filing the recess region,
wherein the upper pattern includes a protrusion protruding upwardly from a top surface of the interlayer insulating layer.