US 11,869,835 B2
Semiconductor package
Seokhyun Lee, Hwaseong-si (KR); Jongyoun Kim, Seoul (KR); Yeonho Jang, Goyang-si (KR); and Jaegwon Jang, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 22, 2022, as Appl. No. 17/892,215.
Application 17/892,215 is a continuation of application No. 16/884,212, filed on May 27, 2020, granted, now 11,456,241.
Claims priority of application No. 10-2019-0127858 (KR), filed on Oct. 15, 2019.
Prior Publication US 2022/0406702 A1, Dec. 22, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H01L 23/49816 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor package, the method comprising:
forming a first insulating layer, the first insulating layer having a first opening;
forming a pad having an upper portion and a lower portion, the upper portion of the pad being located on the first insulating layer and the lower portion of the pad being located in the first opening;
forming a second insulating layer on the first insulating layer and the pad;
forming a redistribution structure on the second insulating layer;
attaching a semiconductor chip on the redistribution structure; and
forming a bump contacting a lower surface of the lower portion of the pad;
wherein the upper portion having a greater horizontal maximum length than the lower portion, and
wherein a lower surface of the first insulating layer and the lower surface of the lower portion of the pad are coplanar.