US 11,869,811 B2
Semiconductor device and method of manufacturing the same
Wonhyuk Lee, Incheon (KR); Jeongyun Lee, Yongin-si (KR); Yongseok Lee, Hwaseong-si (KR); Bosoon Kim, Hwaseong-si (KR); Sangduk Park, Hwaseong-si (KR); Seungchul Oh, Seoul (KR); and Youngmook Oh, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 27, 2021, as Appl. No. 17/562,802.
Application 17/562,802 is a continuation of application No. 16/503,728, filed on Jul. 5, 2019, granted, now 11,211,294.
Application 16/503,728 is a continuation of application No. 15/405,420, filed on Jan. 13, 2017, granted, now 10,366,927, issued on Jul. 30, 2019.
Claims priority of application No. 10-2016-0004336 (KR), filed on Jan. 13, 2016.
Prior Publication US 2022/0122891 A1, Apr. 21, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/762 (2006.01); H01L 29/08 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 21/823481 (2013.01) [H01L 21/76224 (2013.01); H01L 21/823418 (2013.01); H01L 27/088 (2013.01); H01L 29/0847 (2013.01); H01L 21/823431 (2013.01); H01L 21/823456 (2013.01); H01L 21/823814 (2013.01); H01L 27/0886 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a device isolation layer provided on a substrate, the device isolation layer defining a first sub-active pattern and a second sub-active pattern, the first and second sub-active patterns extending in a first direction and spaced apart from each other in the first direction;
a first gate electrode and a second gate electrode crossing the first sub-active pattern and the second sub-active pattern, respectively; and
an isolation structure provided on the device isolation layer between the first and second sub-active patterns,
wherein the device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns,
wherein the isolation structure covers a top surface of the diffusion break region,
wherein the isolation structure comprises:
an isolation pattern extending in a second direction crossing the first direction; and
isolation spacers provided on both sidewalls of the isolation pattern, respectively,
wherein the gate electrodes and the isolation pattern are formed of different materials from each other, and
wherein the isolation pattern has a first width that is the maximum width in the first direction, the diffusion break region has a second width that is the maximum width in the first direction, and the second width is greater than the first width.
 
7. A semiconductor device comprising:
a first fin-type active pattern formed on a substrate, the first fin-type active pattern extending in a first direction;
a second fin-type active pattern formed on the substrate, the second fin-type active pattern extending in the first direction;
the first and second fin-type active patterns spaced apart from each other in the first direction;
a device isolation layer disposed between the first and second fin-type active patterns, the device isolation layer being an insulator;
a first gate electrode and a second gate electrode crossing the respective first and second fin-type active patterns;
a first gate spacer disposed on one sidewall of the first gate electrode;
a second gate spacer disposed on the one sidewall of the second gate electrode; and
an isolation structure disposed on the device isolation layer between the first and second fin-type active patterns,
wherein the isolation structure comprises:
an isolation pattern extending in a second direction crossing the first direction; and
isolation spacers provided on both sidewalls of the isolation pattern, respectively,
wherein with respect to a vertical cross section taken along the first direction, the isolation pattern has a top surface at a location directly above a center of the device isolation layer at least as high as top surfaces of the first and second gate electrodes,
wherein the gate electrodes and the isolation pattern are formed of different materials from each other, and
wherein the isolation pattern has a first width that is the maximum width in the first direction, the diffusion break region has a second width that is the maximum width in the first direction, and the second width is greater than the first width.
 
13. A semiconductor device comprising:
a first fin-type active pattern formed on a substrate, the first fin-type active pattern extending in a first direction;
a second fin-type active pattern formed on the substrate, the second fin-type active pattern extending in the first direction;
the first and second fin-type active patterns spaced apart from each other in the first direction;
a device isolation layer disposed between the first and second fin-type active patterns, the device isolation layer being an insulator;
a first gate electrode and a second gate electrode crossing the respective first and second fin-type active patterns;
a first gate spacer disposed on one sidewall of the first gate electrode;
a second gate spacer disposed on the one sidewall of the second gate electrode; and
an isolation structure disposed on the device isolation layer between the first and second fin-type active patterns,
wherein the isolation structure comprises:
an isolation pattern extending in a second direction crossing the first direction; and
isolation spacers provided on both sidewalls of the isolation pattern, respectively,
wherein the gate electrodes and the isolation pattern are formed of different materials from each other, and
wherein the isolation pattern has a first width that is the maximum width in the first direction, the diffusion break region has a second width that is the maximum width in the first direction, and the second width is greater than the first width.