US 11,869,803 B2
Single crystalline silicon stack formation and bonding to a CMOS wafer
Si-Woo Lee, Boise, ID (US); and Byung Yoon Kim, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 20, 2022, as Appl. No. 17/749,282.
Application 17/749,282 is a continuation of application No. 17/086,536, filed on Nov. 2, 2020, granted, now 11,342,218.
Prior Publication US 2022/0277987 A1, Sep. 1, 2022
Int. Cl. H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 25/18 (2023.01); H01L 25/00 (2006.01)
CPC H01L 21/76251 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02598 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 21/02381 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A device, comprising:
a number of CMOS components formed on a first substrate;
a second substrate attached to the first substrate, wherein the second substrate comprises:
a first layer of single crystal silicon germanium formed on a surface of the second substrate;
a first layer of single crystal silicon formed on a surface of the single crystal silicon germanium; and
repeating iterations of layers of single crystal silicon germanium and single crystal silicon forming a vertical stack of alternating single crystal silicon and single crystal silicon germanium layers.