US 11,869,622 B2
Memory with fine grain architectures
Brent Keeth, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 5, 2021, as Appl. No. 17/494,606.
Claims priority of provisional application 63/107,278, filed on Oct. 29, 2020.
Prior Publication US 2022/0139426 A1, May 5, 2022
Int. Cl. G11C 5/06 (2006.01); G11C 5/02 (2006.01); G11C 5/14 (2006.01)
CPC G11C 5/063 (2013.01) [G11C 5/025 (2013.01); G11C 5/148 (2013.01)] 32 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device, wherein the memory device comprises a plurality of memory arrays that include a first memory array and a second memory array stacked on the first memory array, one or more column positions are common to each memory array of the plurality of memory arrays;
a first organic substrate comprising a plurality of first conductive lines arranged with a first pitch, the plurality of first conductive lines configured to power one or more components of the memory device; and
a second organic substrate coupled with the memory device and the first organic substrate, the second organic substrate comprising a plurality of second conductive lines arranged with a second pitch smaller than the first pitch, wherein the plurality of second conductive lines routed through the second organic substrate are configured to couple the memory device with a host device.