US 11,869,601 B2
Memory system and memory controller
Kenji Sakurada, Yamato (JP); Naomi Takeda, Yokohama (JP); Masanobu Shirakawa, Chigasaki (JP); and Marie Takada, Yokohama (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Nov. 7, 2022, as Appl. No. 18/053,271.
Application 18/053,271 is a continuation of application No. 17/117,937, filed on Dec. 10, 2020, granted, now 11,545,223.
Claims priority of application No. 2020-096428 (JP), filed on Jun. 2, 2020.
Prior Publication US 2023/0088099 A1, Mar. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01); G06F 3/06 (2006.01); G11C 16/34 (2006.01); H10B 69/00 (2023.01)
CPC G11C 16/26 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01); H10B 69/00 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A method of controlling a memory device,
the memory device including:
a first memory including a storage area, the first memory being a nonvolatile memory;
a first data latch group used for input and output of data to and from the first memory; and
at least one second data latch group in which stored data is maintained when the data is read from the first memory, and
the method comprising:
storing management information in the at least one second data latch group when or before executing a read process for the data from the first memory, the management information being in a second memory and used for reading the data; and
executing the read process.