US 11,869,597 B2
Semiconductor storage device including a voltage generator for applying first and second intermediate voltages to an adjacent word line in a program operation
Takeshi Nakano, Kawasaki (JP); Yuzuru Shibazaki, Fujisawa (JP); Hideyuki Kataoka, Yokohama (JP); Junichi Sato, Yokohama (JP); and Hiroki Date, Chigasaki (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 1, 2021, as Appl. No. 17/464,297.
Claims priority of application No. 2021-045259 (JP), filed on Mar. 18, 2021.
Prior Publication US 2022/0301630 A1, Sep. 22, 2022
Int. Cl. G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 29/42 (2006.01); G11C 16/08 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 29/42 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor storage device comprising:
a plurality of planes each including a memory cell array configured by a plurality of memory cells, word lines connected to gates of the plurality of memory cells, and bit lines electrically connected to one ends of the plurality of memory cells via selection gate transistors respectively connected to the one ends of the plurality of memory cells;
a voltage generation circuit capable of generating a voltage supplied to one or more of the memory cell arrays respectively included in the plurality of planes, the voltage generation circuit supplying a program voltage to a writing target selected word line in a program period and applying a first intermediate voltage to an adjacent word line adjacent to the selected word line in a former half of the program period and applying a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period;
a discharge circuit provided on a path between the voltage generation circuit and the selected word line and configured to feed a discharge current from the selected word line in a period corresponding to a period in which the second intermediate voltage is applied to the adjacent word line; and
a control circuit configured to set a discharge characteristic of the discharge circuit according to a number of the planes to which the program voltage is simultaneously supplied from the voltage generation circuit.