US 11,869,593 B2
Semiconductor memory device
Katsuaki Sakurai, Yokohama Kanagawa (JP); Osamu Kobayashi, Sagamihara Kanagawa (JP); and Tomonori Kurosawa, Zama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jan. 14, 2022, as Appl. No. 17/575,724.
Claims priority of application No. 2021-093006 (JP), filed on Jun. 2, 2021.
Prior Publication US 2022/0392531 A1, Dec. 8, 2022
Int. Cl. G11C 16/08 (2006.01); G11C 16/26 (2006.01); H10B 41/41 (2023.01); H10B 43/40 (2023.01)
CPC G11C 16/08 (2013.01) [G11C 16/26 (2013.01); H10B 41/41 (2023.02); H10B 43/40 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a memory cell;
a first word line coupled between a control end of the memory cell and a first node;
a resistance element coupled between the first node and a second node;
a control circuit configured to output a voltage to the second node;
a first switch coupled between the first node and a third node;
a second switch coupled between the second node and the third node; and
a comparator including an input end that receives a signal corresponding to a voltage of the third node.