US 11,869,577 B2
Decoding architecture for memory devices
Paolo Fantini, Vimercate (IT); Enrico Varesi, Milan (IT); Lorenzo Fratin, Buccinasco (IT); and Fabio Pellizzer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 24, 2023, as Appl. No. 18/100,802.
Application 18/100,802 is a continuation of application No. 17/231,657, filed on Apr. 15, 2021, granted, now 11,587,606.
Prior Publication US 2023/0238050 A1, Jul. 27, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/408 (2006.01); G11C 5/06 (2006.01); G11C 11/4074 (2006.01)
CPC G11C 11/4085 (2013.01) [G11C 5/06 (2013.01); G11C 11/4074 (2013.01); G11C 11/4087 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first pillar extending through a stack of materials comprising a first word line plate comprising a first plurality of word lines and a second word line plate comprising a second plurality of word lines, wherein the first pillar is coupled with a first memory cell located between the first pillar and a first word line of the first plurality of word lines;
a second pillar extending though the stack of materials, wherein the second pillar is coupled with a second memory cell located between the second pillar and a second word line of the second plurality of word lines; and
an electrode coupled with the first word line plate and the second word line plate, the electrode operable to concurrently activate the first word line and the second word line to access the first memory cell and the second memory cell.