US 11,869,444 B2
Display device having a clock training with a plurality of signal levels and driving method thereof
Chae Hee Park, Yongin-si (KR); Jong Soo Kim, Yongin-si (KR); Heen Dol Kim, Yongin-si (KR); Ji Ye Lee, Yongin-si (KR); and Young Suk Jung, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Jul. 28, 2022, as Appl. No. 17/815,590.
Claims priority of application No. 10-2021-0160770 (KR), filed on Nov. 19, 2021.
Prior Publication US 2023/0162689 A1, May 25, 2023
Int. Cl. G09G 3/3275 (2016.01)
CPC G09G 3/3275 (2013.01) [G09G 2310/0272 (2013.01); G09G 2310/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display device comprising:
a timing controller configured to supply a clock training signal through a data clock signal line in a first period of one frame period, and supply image data through the data clock signal line in a second period of the one frame period;
a data driver configured to generate a clock signal, based on the clock training signal in a clock training period in the first period, and generate a data signal, based on the clock signal and the image data in the second period; and
a pixel unit configured to display an image, based on the data signal,
wherein the clock training signal includes a plurality of signal levels, and
wherein the data driver determines the clock training period, based on the signal levels of the clock training signal,
wherein the clock training signal includes a first bit and a second bit, which correspond to each of the signal levels, and
wherein the data driver determines the clock training period, based on the first bit of the clock training signal.