CPC G09G 3/3275 (2013.01) [G09G 2310/0272 (2013.01); G09G 2310/08 (2013.01)] | 19 Claims |
1. A display device comprising:
a timing controller configured to supply a clock training signal through a data clock signal line in a first period of one frame period, and supply image data through the data clock signal line in a second period of the one frame period;
a data driver configured to generate a clock signal, based on the clock training signal in a clock training period in the first period, and generate a data signal, based on the clock signal and the image data in the second period; and
a pixel unit configured to display an image, based on the data signal,
wherein the clock training signal includes a plurality of signal levels, and
wherein the data driver determines the clock training period, based on the signal levels of the clock training signal,
wherein the clock training signal includes a first bit and a second bit, which correspond to each of the signal levels, and
wherein the data driver determines the clock training period, based on the first bit of the clock training signal.
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