US 11,869,119 B2
Controlling coarse pixel size from a stencil buffer
Karthik Vaidyanathan, Berkeley, CA (US); Prasoonkumar Surti, Folsom, CA (US); Hugues Labbe, Folsom, CA (US); Atsuo Kuwahara, Portland, OR (US); Sameer Kp, Bangalore (IN); Jonathan Kennedy, Bristol (GB); Murali Ramadoss, Folsom, CA (US); Michael Apodaca, Folsom, CA (US); and Abhishek Venkatesh, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 7, 2022, as Appl. No. 17/666,193.
Application 17/666,193 is a continuation of application No. 16/919,839, filed on Jul. 2, 2020, granted, now 11,244,479.
Application 16/919,839 is a continuation of application No. 16/142,866, filed on Sep. 26, 2018, granted, now 10,706,591, issued on Jul. 7, 2020.
Application 16/142,866 is a continuation of application No. 15/483,701, filed on Apr. 10, 2017, granted, now 10,109,078, issued on Oct. 23, 2018.
Prior Publication US 2022/0262047 A1, Aug. 18, 2022
Int. Cl. G06T 1/20 (2006.01); G06T 11/00 (2006.01); G06T 1/60 (2006.01); G06T 15/00 (2011.01)
CPC G06T 11/001 (2013.01) [G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01); G06T 2210/52 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A system comprising:
a display;
a graphics pipeline coupled to the display; and
logic to:
identify a two-dimensional (2D) texture value,
determine, based on the 2D texture value, a size of a group of pixels that are to share a single pixel shader evaluation, and
conduct the single pixel shader evaluation to generate a value for the group of pixels.