US 11,868,874 B2
Two-dimensional array-based neuromorphic processor and implementing method
Sungho Kim, Yongin-si (KR); Cheheung Kim, Yongin-si (KR); and Jaeho Lee, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 10, 2023, as Appl. No. 18/120,137.
Application 18/120,137 is a continuation of application No. 16/274,547, filed on Feb. 13, 2019, granted, now 11,663,451.
Claims priority of application No. 10-2018-0104731 (KR), filed on Sep. 3, 2018.
Prior Publication US 2023/0214637 A1, Jul. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/063 (2023.01); G06F 7/523 (2006.01); G06F 7/50 (2006.01)
CPC G06N 3/063 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 2207/4824 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A two-dimensional (2D) array-based neuromorphic processor, comprising:
axon circuits, each of n axon circuits of the axon circuits being configured to receive a first input corresponding to a respectively different bit from among bits of an n-bit activation;
n first direction lines extending in a first direction from the axon circuits;
m second direction lines intersecting the first direction lines;
synapse circuits disposed at intersections of the first direction lines and the second direction lines, each of the synapse circuits being configured to:
store a second input corresponding to a respectively different bit from among bits of an m-bit weight, and
output an operation value of a corresponding first input and the second input; and
neuron circuits connected to the first direction lines or the second direction lines, each of the neuron circuits being configured to:
receive respective operation values output from at least one of the synapse circuits, based on time information assigned individually to the synapse circuits, and
perform an arithmetic operation by using the respective operation values,
wherein n and m are natural numbers, and at least one of n or m is greater than 1,
wherein the neuron circuits collectively generate a multiplication result between the n-bit activation and the m-bit weight,
wherein at least some of the neuron circuits respectively include a different single adder, wherein each of the single adders is configured to calculate one of a plurality of bits the multiplication result by performing an addition operation, and
wherein respective synapse circuits provided on a same line among the first direction lines are assigned with same time information, and respective synapse circuits provided on different lines among the first direction lines are assigned with different time information.