US 11,868,740 B2
Ternary logic circuit device
Seokhyeong Kang, Pohang-si (KR); Sunmean Kim, Pohang-si (KR); Sunghye Park, Daegu (KR); and SungYun Lee, Busan (KR)
Assigned to Postech Research and Business Development Foundation, Pohang-si (KR)
Filed by POSTECH Research and Business Development Foundation, Pohang-si (KR)
Filed on Sep. 29, 2021, as Appl. No. 17/489,629.
Claims priority of application No. 10-2021-0055863 (KR), filed on Apr. 29, 2021.
Prior Publication US 2022/0350568 A1, Nov. 3, 2022
Int. Cl. G06F 7/502 (2006.01); H03K 19/173 (2006.01); H03K 19/094 (2006.01)
CPC G06F 7/502 (2013.01) [H03K 19/173 (2013.01); H03K 19/094 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A circuit comprising:
a first full adder;
a second full adder;
a first half adder;
a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder;
a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder;
a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder; and
a third half adder configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder,
wherein the third full adder, the second half adder, and the third half adder are configured to output voltage signals corresponding to a sum of logical values indicated by input signals applied to the first full adder, the second full adder, and the first half adder,
wherein the first full adder, the second full adder, the third full adder, and the fourth full adder are ternary full adders (TFAs), and
wherein the first half adder, the second half adder, and the third half adder are ternary half adders (THAs).