US 11,868,650 B2
Apparatus with combinational access mechanism and methods for operating the same
Hyun Yoo Lee, Boise, ID (US); and Kang-Yong Kim, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 11, 2022, as Appl. No. 17/662,993.
Application 17/662,993 is a continuation of application No. 17/022,551, filed on Sep. 16, 2020, granted, now 11,360,695.
Prior Publication US 2022/0269432 A1, Aug. 25, 2022
Int. Cl. G06F 3/00 (2006.01); G06F 3/06 (2006.01); G11C 11/406 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 11/406 (2013.01); G11C 11/4082 (2013.01); G11C 11/4096 (2013.01); G11C 2211/4062 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first memory circuit having a first set of performance measures that include at least a first type and a second type, wherein the first memory circuit is configured to increase the first type of performance measure;
a second memory circuit having a second set of performance measures that include the first type and the second type, wherein the second memory circuit is configured to increase the second type of performance measure:
a shared interface connected to the first and second memory circuits, wherein the shared interface provides a common input, a common output, or both for the first and second memory circuits; and
a selection interface configured to select between the first memory circuit and the second memory circuit to perform a memory operation.