US 11,868,648 B2
Memory system
Kensuke Yamamoto, Yokohama Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jan. 14, 2022, as Appl. No. 17/575,749.
Application 17/575,749 is a continuation of application No. PCT/JP2019/036211, filed on Sep. 13, 2019.
Prior Publication US 2022/0137870 A1, May 5, 2022
Int. Cl. G11C 7/22 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 13/1668 (2013.01); G11C 7/1063 (2013.01); G11C 7/22 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A memory system comprising:
a semiconductor memory; and
a controller configured to provide an instruction to read data from the semiconductor memory,
the semiconductor memory including,
a memory cell transistor configured to store data;
an output circuit configured to perform a process for data read from the memory cell transistor to be output to the controller; and
a data generator configured to generate first data,
wherein when the data is read,
the controller outputs a first signal to the semiconductor memory within a first period in which the output circuit is performing the process,
the semiconductor memory generates a second signal based on the first signal, and outputs the first data along with the second signal to the controller in the first period and a second period, and
after the second period has lapsed, the semiconductor memory outputs the data read from the memory cell transistor along with the second signal to the controller.