CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] | 17 Claims |
1. A nonvolatile memory device comprising:
a memory block including a first memory area connected to a first word line; and
control logic comprising:
an on-chip valley search (OVS) circuit configured to perform an OVS sensing operation on the memory block; and
a first buffer memory configured to store at least one variation table including variation information of a threshold voltage of memory cells connected to the first word line, obtained from the OVS sensing operation,
wherein the control logic is configured to:
perform a first reading operation on the first memory area in response to a first read command applied by a memory controller, the first reading operation including a first OVS sensing operation performed at a first OVS sensing level and a first main sensing operation performed at a first main sensing level reflecting the variation information in response to the first read command.
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