US 11,868,285 B2
Memory controller configured to transmit interrupt signal if volatile memory has no data corresponding to address requested from source
Toshio Fujisawa, Yokohama Kanagawa (JP); Nobuhiro Kondo, Yokohama Kanagawa (JP); Shoji Sawamura, Yokohama Kanagawa (JP); Kenichi Maeda, Kamakura Kanagawa (JP); and Atsushi Kunimatsu, Funabashi Chiba (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Nov. 18, 2022, as Appl. No. 17/990,169.
Application 17/990,169 is a continuation of application No. 17/155,415, filed on Jan. 22, 2021, granted, now 11,537,536.
Application 17/155,415 is a continuation of application No. 16/023,458, filed on Jun. 29, 2018, granted, now 10,929,315, issued on Feb. 23, 2021.
Application 16/023,458 is a continuation of application No. 14/808,431, filed on Jul. 24, 2015, granted, now 10,042,786, issued on Aug. 7, 2018.
Claims priority of application No. 2015-047251 (JP), filed on Mar. 10, 2015.
Prior Publication US 2023/0078983 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G06F 13/28 (2006.01); G11C 11/00 (2006.01); G11C 5/04 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 13/28 (2013.01); G11C 11/005 (2013.01); G11C 5/04 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method of controlling a nonvolatile memory and a volatile memory, said method comprising:
configuring the volatile memory to cache a part of data stored in the nonvolatile memory; and
in response to receiving, from a requester, a first request that includes an address,
in a case where first data is not cached in the volatile memory, the first data corresponding to the address included in the first request,
reading the first data from the nonvolatile memory;
storing the read first data into the volatile memory; and
upon the first data being stored into the volatile memory, sending, to the requester, first information indicating that the first data has been cached into the volatile memory.