US 10,892,763 B1
Second-order clock recovery using three feedback paths
Yasuo Hidaka, Cupertino, CA (US); and Junqing (Phil) Sun, Fremont, CA (US)
Assigned to Credo Technology Group Limited, Grand Cayman (KY)
Filed by Credo Technology Group Limited, Grand Cayman (KY)
Filed on May 14, 2020, as Appl. No. 16/874,261.
Int. Cl. H03L 7/08 (2006.01); H03L 7/091 (2006.01); G06F 1/08 (2006.01); H03L 7/07 (2006.01)
CPC H03L 7/0807 (2013.01) [G06F 1/08 (2013.01); H03L 7/07 (2013.01); H03L 7/091 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An integrated receiver circuit that comprises:
a fractional-N phase lock loop that provides a clock signal;
a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal;
a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal;
a timing error estimator that produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal;
at least one feedback path coupling the timing error signal to the phase interpolator, the at least one feedback path using a phase error accumulator to minimize a phase component of the estimated timing error and using a frequency error accumulator to minimize a frequency offset component of the estimated timing error;
and
an additional feedback path coupling the timing error signal to the fractional-N phase lock loop to minimize the frequency offset component of the estimated timing error in parallel with said at least one feedback path.