US 10,892,760 B1
Dynamic transistor gate overdrive for input/output (I/O) drivers and level shifters
Sumit Rao, San Diego, CA (US); Wilson Jianbo Chen, San Diego, CA (US); and Chiew-Guan Tan, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Oct. 15, 2019, as Appl. No. 16/653,391.
Int. Cl. H03K 19/0175 (2006.01); H03K 19/0185 (2006.01); H03K 19/003 (2006.01)
CPC H03K 19/018521 (2013.01) [H03K 19/00384 (2013.01); H03K 19/017509 (2013.01); H03K 19/017545 (2013.01)] 27 Claims
OG exemplary drawing
 
1. An apparatus for generating an output voltage signal based on an input voltage signal, comprising:
a first field effect transistor (FET) including a first gate configured to receive a first gate voltage based on the input voltage signal;
a second FET including a second gate configured to receive a second gate voltage based on the input voltage signal, wherein the first and second FETs are coupled in series between a first voltage rail and a second voltage rail, and wherein the output voltage signal is produced at an output node between the first and second FETs;
a gate overdrive circuit configured to temporarily reduce the first gate voltage during a first portion of a transition of the output voltage signal from a logic low level to a logic high level; and
a third FET coupled between the output node and the first FET, wherein the third FET includes a third gate configured to receive a third gate voltage, and wherein the gate overdrive circuit is configured to temporarily reduce the third gate voltage substantially coincidental with the reduction of the first gate voltage of the first FET.