US 10,892,744 B2
Correcting duty cycle and compensating for active clock edge shift
Michael Koch, Ehningen (DE); Matthias Ringe, Tuebingen (DE); Andreas Arp, Nufringen (DE); and Fatih Cilek, Boeblingen (DE)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 25, 2017, as Appl. No. 15/714,012.
Prior Publication US 2019/0097617 A1, Mar. 28, 2019
Int. Cl. H03K 3/017 (2006.01); H03K 5/04 (2006.01); H03K 7/08 (2006.01); H03K 5/156 (2006.01); H03K 21/08 (2006.01); H03K 5/133 (2014.01); H03K 5/00 (2006.01)
CPC H03K 5/1565 (2013.01) [H03K 5/133 (2013.01); H03K 21/08 (2013.01); H03K 2005/00065 (2013.01); H03K 2005/00071 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A system comprising:
at least one control circuit logically configured to receive duty cycle correction control signals and logically configured to output at least one first adjustment signal, at least one second adjustment signal, at least one first correction signal, and at least one second correction signal, and wherein the at least one control circuit is configured to maintain a constant delay between at least one adjustment circuit and at least one correction circuit;
the at least one adjustment circuit logically coupled to the at least one control circuit and logically configured to change a duty cycle value of an input clock signal in response to receiving the at least one first adjustment signal on a first adjustment input of the at least one adjustment circuit and the at least one second adjustment signal on a second adjustment input of the at least one adjustment circuit, wherein changing a duty cycle value comprises introducing a first delay in the input clock signal, resulting in a second clock signal;
the at least one correction circuit logically coupled to the at least one control circuit, logically coupled to the at least one adjustment circuit, and logically configured to compensate for a shift of an active clock edge of the input clock signal in response to receiving the at least one first correction signal on a first correction input of the at least one correction circuit and the at least one second correction signal on a second correction input of the at least one correction circuit, wherein compensating for a shift of an active clock edge comprises introducing a second delay in the second clock signal, resulting in a corrected output clock signal;
wherein the value of the second delay is based on the constant delay, the first delay, and the shift;
wherein the difference between the input clock signal and the corrected output clock signal is the constant delay;
wherein one of the set of the at least one adjustment circuit and the at least one correction circuit is logically configured to transmit the corrected output clock signal, in response to the at least one adjustment circuit receiving the at least one first adjustment signal and the at least one second adjustment signal and in response to the at least one correction circuit receiving the at least one first correction signal and the at least one second correction signal.