US 10,892,675 B2
Voltage converting circuit and control circuit thereof
Ching-Tsan Lee, Hsinchu County (TW); Pei-Ting Yang, Hsinchu County (TW); and Ming-Hung Chien, Hsinchu County (TW)
Assigned to Excelliance MOS Corporation, Hsinchu County (TW)
Filed by Excelliance MOS Corporation, Hsinchu County (TW)
Filed on Aug. 20, 2018, as Appl. No. 16/104,957.
Claims priority of application No. 107118986 A (TW), filed on Jun. 1, 2018.
Prior Publication US 2019/0372452 A1, Dec. 5, 2019
Int. Cl. G05F 1/569 (2006.01); H02M 1/08 (2006.01); H02H 3/00 (2006.01); H03K 17/081 (2006.01); H02H 3/18 (2006.01); H03K 17/0412 (2006.01)
CPC H02M 1/08 (2013.01) [G05F 1/569 (2013.01); H02H 3/003 (2013.01); H02H 3/18 (2013.01); H03K 17/0412 (2013.01); H03K 17/08104 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A control circuit for controlling a driving switch which has two terminals respectively receiving an input voltage and an output voltage, the control circuit comprising:
a comparator, receiving the input voltage and the output voltage and comparing a voltage level of the input voltage with a voltage level of the output voltage to generate a comparison signal;
a clock generator, coupled to the comparator to receive the comparison signal and generating a clock signal according to the comparison signal, so as to enable the clock signal to have a first frequency in a first time interval and to have a second frequency in a second time interval, wherein the first frequency is higher than the second frequency, and the first time interval occurs before the second time interval; and
a boost circuit, coupled to the clock generator and a control terminal of the driving switch to receive the clock signal, pulling up a voltage level of a control signal of the driving switch according to a first driving capability in the first time interval and generating the control signal according to a second driving capability in the second time interval, wherein the first driving capability is greater than the second driving capability,
wherein the clock generator comprises:
a mode signal generator, coupled to the comparator, receiving the comparison signal and performing a timing operation according to the comparison signal, so as to generate a mode signal; and
an oscillator, coupled to the mode signal generator, receiving the mode signal and adjusting a frequency of the clock signal according to the mode signal,
wherein the mode signal generator comprises:
a timer, performing the timing operation based on the comparison signal to generate a timing result; and
a logic operator, coupled to the timer and executing a logic operation according to the comparison signal and the timing result to generate the mode signal.