US 10,892,413 B2
Integration of confined phase change memory with threshold switching material
Robert L. Bruce, White Plains, NY (US); Fabio Carta, White Plains, NY (US); Wanki Kim, Westchester, NY (US); and Chung H. Lam, Peekskill, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jan. 17, 2017, as Appl. No. 15/408,392.
Prior Publication US 2018/0205017 A1, Jul. 19, 2018
Int. Cl. H01L 45/00 (2006.01); H01L 27/24 (2006.01)
CPC H01L 45/1683 (2013.01) [H01L 27/2409 (2013.01); H01L 27/2427 (2013.01); H01L 27/2481 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/1293 (2013.01); H01L 45/144 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A phase change memory array comprising:
a plurality of bottom electrodes;
a plurality of top electrodes positioned along a bit line direction;
a plurality of memory pillars, each of the memory pillars including phase change material surrounded by a dielectric casing, the dielectric casing including a casing lip in physical contact with the phase change material, the dielectric casing and casing lip forming an L-shaped cross section defining a space between the dielectric casing and the phase change material, the phase change material positioned between, and in series circuit with, a respective bottom electrode from the plurality of bottom electrodes and a respective top electrode from the plurality of top electrodes, and a metallic liner positioned over and in contact with the casing lip and inside the space between the dielectric casing and the phase change material extending vertically from the casing lip along an area defined by the dielectric casing and the phase change material; and
a continuous layer of unitary selector material positioned parallel lengthwise to the bit line direction and positioned between the memory pillars and the plurality of bottom electrodes, the selector material configured to conduct electricity only when a voltage across the selector material exceeds a voltage threshold; and
wherein each of the bottom electrodes is physically and electrically isolated from one another by a dielectric substrate and the continuous layer of selector material positioned between the memory pillars and the plurality of bottom electrodes.