US 10,892,368 B2
Nanosheet transistor having abrupt junctions between the channel nanosheets and the source/drain extension regions
Choonghyun Lee, Rensselaer, NY (US); Kangguo Cheng, Schenectady, NY (US); Juntao Li, Cohoes, NY (US); and Shogo Mochizuki, Clifton Park, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on May 8, 2019, as Appl. No. 16/406,390.
Prior Publication US 2020/0357931 A1, Nov. 12, 2020
Int. Cl. H01L 29/786 (2006.01); H01L 29/775 (2006.01); H01L 29/161 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 29/0665 (2013.01); H01L 29/161 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method of performing fabrication operations to form a nanosheet field effect transistor (FET) device, wherein the fabrication operations include:
forming a nanosheet stack over a substrate;
wherein the nanosheet stack comprises a plurality of channel nanosheets;
wherein the plurality of channel nanosheets includes a first channel nanosheet having a first end region, a second end region, and a central region positioned between the first end region and the second end region;
wherein the first end region, the second end region, and the central region each comprises a first type of semiconductor material;
wherein, when the first type of semiconductor material is at a first temperature, the first type of semiconductor material has a first diffusion coefficient for a dopant; and
converting the central region to a second type of semiconductor material;
wherein, when the second type of semiconductor material is at the first temperature, the second type of semiconductor material has a second diffusion coefficient for the dopant.