US 10,892,366 B2
Thin film transistor and vertical non-volatile memory device including transition metal-induced polycrystalline metal oxide channel layer
Jae Kyeong Jeong, Seoul (KR); Yun Heub Song, Seoul (KR); Chang Hwan Choi, Seoul (KR); and Hyeon Joo Seul, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-Si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 24, 2019, as Appl. No. 16/450,218.
Claims priority of application No. 10-2018-0072751 (KR), filed on Jun. 25, 2018.
Prior Publication US 2019/0393353 A1, Dec. 26, 2019
Int. Cl. H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 27/11558 (2017.01); H01L 27/11597 (2017.01); H01L 27/1156 (2017.01); H01L 27/11582 (2017.01); H01L 27/24 (2006.01); H01L 27/11514 (2017.01); H01L 27/11553 (2017.01); H01L 27/11556 (2017.01); H01L 27/11551 (2017.01); H01L 27/1158 (2017.01)
CPC H01L 29/7869 (2013.01) [H01L 27/1156 (2013.01); H01L 27/1158 (2013.01); H01L 27/11514 (2013.01); H01L 27/11551 (2013.01); H01L 27/11553 (2013.01); H01L 27/11556 (2013.01); H01L 27/11558 (2013.01); H01L 27/11582 (2013.01); H01L 27/11597 (2013.01); H01L 27/249 (2013.01); H01L 27/2481 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a liner pattern including a transition metal on the substrate;
a polycrystalline metal oxide pattern on the liner pattern;
an insulating film extending along a sidewall of the liner pattern, a sidewall of the polycrystalline metal oxide pattern, and an upper surface of the polycrystalline metal oxide pattern; and
a gate electrode on the insulating film.