US 10,892,360 B2
Semiconductor device structure with high voltage device
Hung-Chou Lin, Douliu (TW); Yi-Cheng Chiu, New Taipei (TW); Karthick Murukesan, Hsinchu (TW); Yi-Min Chen, Hsinchu (TW); Shiuan-Jeng Lin, Hsinchu (TW); Wen-Chih Chiang, Hsinchu (TW); Chen-Chien Chang, Zhubei (TW); Chih-Yuan Chan, Kaohsiung (TW); Kuo-Ming Wu, Hsinchu (TW); and Chun-Lin Tsai, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Oct. 29, 2018, as Appl. No. 16/173,721.
Claims priority of provisional application 62/590,808, filed on Nov. 27, 2017.
Prior Publication US 2019/0165167 A1, May 30, 2019
Int. Cl. H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/40 (2006.01)
CPC H01L 29/7816 (2013.01) [H01L 29/0649 (2013.01); H01L 29/0692 (2013.01); H01L 29/0865 (2013.01); H01L 29/0869 (2013.01); H01L 29/0882 (2013.01); H01L 29/0886 (2013.01); H01L 29/402 (2013.01); H01L 29/404 (2013.01); H01L 29/4238 (2013.01); H01L 29/42356 (2013.01); H01L 29/42368 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A high-voltage semiconductor device structure, comprising:
a semiconductor substrate;
a source ring in the semiconductor substrate;
a drain region in the semiconductor substrate;
a doped ring surrounding sides and a bottom of the source ring;
a well region surrounding sides and bottoms of the drain region and the doped ring, wherein the well region has a conductivity type opposite to that of the doped ring;
a conductor electrically connected to the drain region and extending over and across a periphery of the well region; and
a shielding element ring between the conductor and the semiconductor substrate, wherein the shielding element ring extends over and across the periphery of the well region, and wherein the shielding element ring laterally surrounds the well region, the source ring, and the drain region.