US 10,892,342 B2
Semiconductor devices
Wonkeun Chung, Seoul (KR); Jae-Jung Kim, Suwon-si (KR); Jinkyu Jang, Hwaseong-si (KR); Sangyong Kim, Suwon-si (KR); Hoonjoo Na, Hwaseong-si (KR); Dongsoo Lee, Gunpo-si (KR); and Sangjin Hyun, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 27, 2020, as Appl. No. 16/803,130.
Application 16/803,130 is a continuation of application No. 16/592,309, filed on Oct. 3, 2019, granted, now 10,615,264.
Application 16/592,309 is a continuation of application No. 15/938,716, filed on Mar. 28, 2018, granted, now 10,475,898, issued on Nov. 12, 2019.
Claims priority of application No. 10-2017-0115343 (KR), filed on Sep. 8, 2017.
Prior Publication US 2020/0194565 A1, Jun. 18, 2020
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 27/11 (2006.01); H01L 21/28 (2006.01); B82Y 10/00 (2011.01)
CPC H01L 29/42392 (2013.01) [B82Y 10/00 (2013.01); H01L 21/28088 (2013.01); H01L 21/28114 (2013.01); H01L 27/1104 (2013.01); H01L 29/0669 (2013.01); H01L 29/0673 (2013.01); H01L 29/40114 (2019.08); H01L 29/42372 (2013.01); H01L 29/42376 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing semiconductor device, comprising:
stacking sacrificial layers and semiconductor layers on a substrate alternately;
patterning the sacrificial layers and the semiconductor layers to form an active pattern;
forming a first sacrificial gate pattern on the active pattern;
forming a pair of source/drain patterns on opposite sides of the first sacrificial gate pattern, respectively, the semiconductor layers being interposed between the pair of source/drain patterns to connect them;
removing the first sacrificial gate pattern to form a first space and to expose the sacrificial layers;
removing the exposed sacrificial layers to form second spaces, respectively;
forming a first metal nitride layer in the first and second spaces;
forming a second metal nitride layer containing silicon on the first metal nitride layer in the first space; and
forming a first metal layer on the second metal nitride layer in the first space.
 
11. A method of manufacturing semiconductor device, comprising:
stacking sacrificial layers and semiconductor layers on a substrate alternately;
patterning the sacrificial layers and the semiconductor layers to form a first active pattern and a second active pattern;
forming a first sacrificial gate pattern and a second sacrificial gate pattern on the first and second active patterns, respectively;
removing the first and second sacrificial gate patterns to form a first space and a second space, respectively;
sequentially forming, in the first space, a first metal nitride layer, a second metal nitride layer containing silicon, and a first metal layer; and
sequentially forming, in the second space, a third metal nitride layer containing silicon, and a second metal layer.
 
16. A method of manufacturing semiconductor device, comprising:
stacking sacrificial layers and semiconductor layers on a substrate alternately;
patterning the sacrificial layers and the semiconductor layers to form a first active pattern and a second active pattern;
forming a first sacrificial gate pattern and a second sacrificial gate pattern on the first and second active patterns, respectively;
removing the first and second sacrificial gate patterns to form a first space and a second space, respectively;
sequentially forming, in the first space, a first metal nitride layer, and a second metal nitride layer containing silicon; and
forming a third metal nitride layer containing silicon in the second space,
wherein a silicon concentration of the second metal nitride layer is greater than that of the third metal nitride layer.