US 10,892,325 B2
Vertical field effect transistor with reduced gate to source/drain capacitance
Juntao Li, Cohoes, NY (US); Kangguo Cheng, Schenectady, NY (US); Choonghyun Lee, Rensselaer, NY (US); and Peng Xu, Santa Clara, CA (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 27, 2019, as Appl. No. 16/455,096.
Application 16/455,096 is a continuation of application No. 16/008,687, filed on Jun. 14, 2018, granted, now 10,396,151.
Prior Publication US 2019/0386102 A1, Dec. 19, 2019
Int. Cl. H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0653 (2013.01) [H01L 29/0847 (2013.01); H01L 29/42368 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a fin field effect transistor device, comprising:
forming a vertical fin on a bottom source/drain layer;
reducing the width of the vertical fin to form a thinned vertical fin; and
depositing a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness with at least a portion of a top surface that tapers towards the bottom source/drain layer in a direction towards the thinned vertical fin.