US 10,892,324 B2
Vertical field effect transistor with reduced gate to source/drain capacitance
Juntao Li, Cohoes, NY (US); Kangguo Cheng, Schenectady, NY (US); Choonghyun Lee, Rensselaer, NY (US); and Peng Xu, Santa Clara, CA (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 27, 2019, as Appl. No. 16/455,045.
Application 16/455,045 is a division of application No. 16/008,687, filed on Jun. 14, 2018, granted, now 10,396,151.
Prior Publication US 2019/0386101 A1, Dec. 19, 2019
Int. Cl. H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0653 (2013.01) [H01L 29/0847 (2013.01); H01L 29/42368 (2013.01); H01L 29/66666 (2013.01); H01L 29/7827 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A fin field effect transistor device, comprising:
a bottom source/drain layer on a substrate;
one or more thinned vertical fins on the source/drain layer;
a bottom spacer layer on the bottom source/drain layer, wherein the bottom spacer layer has a non-uniform thickness with a top surface that tapers towards the bottom source/drain layer in a direction towards each of the one or more thinned vertical fins; and
a gate dielectric layer on the bottom spacer layer and sidewalls of each of the one or more thinned vertical fins.