US 10,892,320 B2
Semiconductor devices having stacked trench gate electrodes overlapping a well region
Wen-Shan Lee, Hsinchu (TW); Chung-Yeh Lee, Sinpu Township (TW); and Fu-Hsin Chen, Jhudong Township (TW)
Assigned to Vanguard International Semiconductor Corporation, Hsinchu (TW)
Filed by Vanguard International Semiconductor Corporation, Hsinchu (TW)
Filed on Apr. 30, 2019, as Appl. No. 16/398,866.
Prior Publication US 2020/0350400 A1, Nov. 5, 2020
Int. Cl. H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 21/033 (2006.01); H01L 21/306 (2006.01); H01L 21/265 (2006.01)
CPC H01L 29/0634 (2013.01) [H01L 21/0337 (2013.01); H01L 21/26506 (2013.01); H01L 21/306 (2013.01); H01L 29/4236 (2013.01); H01L 29/66477 (2013.01); H01L 29/78 (2013.01); H01L 29/407 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate having a first conductivity type;
an epitaxial layer having the first conductivity type disposed on the substrate, and a trench is in the epitaxial layer;
a first well region disposed in the epitaxial layer under the trench, and the first well region has a second conductivity type that is different from the first conductivity type;
a first gate electrode disposed in the trench and having the second conductivity type, wherein a doping concentration of the first gate electrode is greater than a doping concentration of the first well region; and
a second gate electrode disposed in the trench on the first gate electrode, wherein the second gate electrode is separated from the first gate electrode by a first insulating layer.