US 10,892,291 B2
Bonding pad architecture using capacitive deep trench isolation (CDTI) structures for electrical connection
Sonarith Chhun, Pontcharra (FR); and Gregory Imbert, Revel (FR)
Assigned to STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed by STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed on Feb. 26, 2019, as Appl. No. 16/285,306.
Application 16/285,306 is a division of application No. 15/707,009, filed on Sep. 18, 2017, abandoned.
Prior Publication US 2019/0189654 A1, Jun. 20, 2019
Int. Cl. H01L 27/146 (2006.01); H01L 21/84 (2006.01); H01L 23/48 (2006.01); H01L 21/762 (2006.01); H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 21/3065 (2006.01); H01L 23/00 (2006.01); H01L 23/552 (2006.01); H01L 29/94 (2006.01)
CPC H01L 27/1464 (2013.01) [H01L 21/3065 (2013.01); H01L 21/76224 (2013.01); H01L 21/84 (2013.01); H01L 23/481 (2013.01); H01L 23/552 (2013.01); H01L 24/00 (2013.01); H01L 24/05 (2013.01); H01L 27/0629 (2013.01); H01L 27/1203 (2013.01); H01L 27/1463 (2013.01); H01L 27/1469 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 29/945 (2013.01); H01L 2224/0509 (2013.01); H01L 2224/05087 (2013.01); H01L 2224/05088 (2013.01); H01L 2224/05093 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05624 (2013.01); H01L 2225/06541 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a plurality of capacitive deep trench isolation structures extending completely through a semiconductor substrate from a front side surface to a back side surface, each capacitive deep trench isolation structure comprising a conductive region insulated from the semiconductor substrate by an insulating liner;
providing a metallization structure at the front side surface of the semiconductor substrate that is electrically connected to first ends of the plurality of capacitive deep trench isolation structures;
recessing the back side surface of the semiconductor substrate to expose second ends of the plurality of capacitive deep trench isolation structures; and
forming a bonding pad structure adjacent the recessed back side surface of the semiconductor substrate, wherein the bonding pad structure is directly physically and electrically connected to the conductive regions at the second ends of the plurality of capacitive deep trench isolation structures and electrically insulated from the semiconductor substrate, wherein forming the bonding pad structure comprises:
depositing a conformal layer of a dielectric material on the recessed back side surface and exposed second ends of the plurality of capacitive deep trench isolation structures;
depositing a conformal layer of an oxide material on the layer of the dielectric material;
planarizing the layer of the oxide material;
opening an aperture extending through at least the layer of the dielectric material which extends on end surfaces of the plurality of capacitive deep trench isolation structures to expose the conductive regions at the second ends of the plurality of capacitive deep trench isolation structures; and
depositing one or more metal materials forming the bonding pad structure within said aperture.