US 10,892,263 B2
Methods of fabricating semiconductor device
Hoi Sung Chung, Suwon-si (KR); Tae Sung Kang, Seoul (KR); Dong Suk Shin, Yongin-si (KR); Kong Soo Lee, Hwaseong-si (KR); and Jun-Won Lee, Asan-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 8, 2019, as Appl. No. 16/270,865.
Claims priority of application No. 10-2018-0068798 (KR), filed on Jun. 15, 2018.
Prior Publication US 2019/0386008 A1, Dec. 19, 2019
Int. Cl. H01L 21/336 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 27/108 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 29/51 (2006.01); H01L 21/311 (2006.01); H01L 21/324 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 21/266 (2006.01); H01L 29/04 (2006.01)
CPC H01L 27/10873 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02667 (2013.01); H01L 21/266 (2013.01); H01L 21/26513 (2013.01); H01L 21/31111 (2013.01); H01L 21/324 (2013.01); H01L 21/76897 (2013.01); H01L 27/10855 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/518 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/045 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, the method comprising:
forming a gate structure on a core-peri region of a substrate, wherein the substrate further comprises a cell region, and the gate structure comprises a conductive film and a gate stack insulation film that comprises a side portion contacting a sidewall of the conductive film and a top portion extending on an upper surface of the conductive film;
forming a gate spacer on a sidewall of the gate structure;
forming a first impurity region adjacent the gate spacer in the core-peri region of the substrate by performing a first ion implantation process;
removing the gate spacer;
forming a second impurity region in the core-peri region of the substrate between the gate structure and the first impurity region by performing a second ion implantation process;
forming a stress film on the gate structure, an upper surface of the first impurity region, and an upper surface of the second impurity region, wherein the stress film contacts the side portion and the top portion of the gate stack insulation film; and
forming a recrystallization region by crystallizing the first impurity region and the second impurity region by performing an annealing process.