US 10,892,239 B1
Bond pad reliability of semiconductor devices
Ramasamy Chockalingam, Singapore (SG); Juan Boon Tan, Singapore (SG); and Ian Melville, Highland, NY (US)
Assigned to GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore (SG)
Filed by GLOBALFOUNDRIES Singapore Pte. Ltd., Singapore (SG)
Filed on Jul. 10, 2019, as Appl. No. 16/508,288.
Int. Cl. H01L 23/34 (2006.01); H01L 23/00 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 24/03 (2013.01); H01L 24/45 (2013.01); H01L 24/85 (2013.01); H01L 2224/0221 (2013.01); H01L 2224/02206 (2013.01); H01L 2224/02215 (2013.01); H01L 2224/03019 (2013.01); H01L 2224/03452 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/83007 (2013.01); H01L 2224/83205 (2013.01); H01L 2924/0509 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/35121 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A bond pad structure comprising:
a dielectric layer;
at least one bond pad in the dielectric layer, having a bond pad top surface;
a passivation layer having an interface with a first portion of the bond pad top surface;
an opening in the passivation layer over the bond pad, wherein the opening has sidewalls;
a low-k barrier layer covering the sidewalls of the opening and a second portion of the bond pad top surface; and
protective structures over the low-k barrier layer at the sidewalls of the opening.