US 10,892,223 B2
Advanced lithography and self-assembled devices
Richard E. Schenker, Portland, OR (US); Robert L. Bristol, Portland, OR (US); Kevin L. Lin, Beaverton, OR (US); Florian Gstrein, Portland, OR (US); James M. Blackwell, Portland, OR (US); Marie Krysak, Portland, OR (US); Manish Chandhok, Beaverton, OR (US); Paul A. Nyhus, Portland, OR (US); Charles H. Wallace, Portland, OR (US); Curtis W. Ward, Hillsboro, OR (US); Swaminathan Sivakumar, Beaverton, OR (US); and Elliot N. Tan, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 16/346,873
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Dec. 23, 2016, PCT No. PCT/US2016/068586
§ 371(c)(1), (2) Date May 1, 2019,
PCT Pub. No. WO2018/118092, PCT Pub. Date Jun. 28, 2018.
Prior Publication US 2020/0066629 A1, Feb. 27, 2020
Int. Cl. H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01)
CPC H01L 23/528 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53238 (2013.01); H01L 27/0886 (2013.01); H01L 29/7848 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by a partial body portion;
a trench isolation layer between the plurality of semiconductor bodies and adjacent to lower portions of the plurality of semiconductor bodies, but not adjacent to upper portions of the plurality of semiconductor bodies, wherein the trench isolation layer is over the partial body portion;
one or more gate electrode stacks on top surfaces and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies and on portions of the trench isolation layer; and
a back end of line (BEOL) metallization layer above the one or more gate electrode stacks, the BEOL metallization layer comprising a plurality of alternating first and second conductive line types along a same direction, wherein a total composition of the first conductive line type is different from a total composition of the second conductive line type.