US 10,892,195 B2
Method and structure for forming a vertical field-effect transistor using a replacement metal gate process
ChoongHyun Lee, Rensselaer, NY (US); Kangguo Cheng, Schenectady, NY (US); and Kisik Choi, Watervliet, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Nov. 14, 2019, as Appl. No. 16/684,126.
Application 16/684,126 is a division of application No. 16/007,546, filed on Jun. 13, 2018, granted, now 10,629,499.
Prior Publication US 2020/0083121 A1, Mar. 12, 2020
Int. Cl. H01L 27/092 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 21/823885 (2013.01) [H01L 21/823814 (2013.01); H01L 21/823842 (2013.01); H01L 21/823878 (2013.01); H01L 27/092 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A vertical transistor device, comprising:
a first plurality of fins in a first device region on a substrate;
a second plurality of fins in a second device region on the substrate;
a first type gate metal layer in the first device region and a second type gate metal layer in the second device region; and
a barrier layer between the first and second device regions;
wherein the barrier layer is disposed between the first type gate metal layer in the first device region and the second type gate metal layer in the second device region;
wherein part of the first type gate metal layer and part the second type gate metal layer contact the barrier layer;
wherein a bottom surface of the barrier layer is coplanar with a bottom surface of the first type gate metal layer and with a bottom surface of the second type gate metal layer; and
wherein the first device region is an n-type transistor region and the second device region is a p-type transistor region.