US 10,892,185 B2
Semiconductor device including a blocking pattern in an interconnection line
Sangjun Park, Seoul (KR); Haewang Lee, Yongin-si (KR); and Jaemyung Choi, Busan (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 15, 2019, as Appl. No. 16/511,019.
Claims priority of application No. 10-2018-0115947 (KR), filed on Sep. 28, 2018.
Prior Publication US 2020/0105578 A1, Apr. 2, 2020
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/528 (2006.01)
CPC H01L 21/7682 (2013.01) [H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first interconnection line having a first end and extending in a first direction;
a first blocking pattern at the first end of the first interconnection line and adjacent to the first interconnection line in the first direction;
a second interconnection line spaced apart from the first interconnection line in a second direction crossing the first direction and extending in the first direction, the second interconnection line having a second end; and
a second blocking pattern at the second end of the second interconnection line and adjacent to the second interconnection line in the first direction,
wherein a width of the first blocking pattern in the first direction is different from a width of the second blocking pattern in the first direction.