US 10,892,169 B2
3D semiconductor device and structure
Zvi Or-Bach, San Jose, CA (US); Brian Cronquist, San Jose, CA (US); and Deepak Sekar, Sunnyvale, CA (US)
Assigned to MONOLITHIC 3D INC., San Jose, CA (US)
Filed by Monolithic 3D Inc., San Jose, CA (US)
Filed on Aug. 28, 2018, as Appl. No. 16/114,211.
Application 16/114,211 is a continuation in part of application No. 15/913,917, filed on Mar. 6, 2018, granted, now 10,115,663.
Application 15/913,917 is a continuation in part of application No. 15/470,872, filed on Mar. 27, 2017, granted, now 9,941,275, issued on Apr. 10, 2018.
Application 15/470,872 is a continuation in part of application No. 13/864,245, filed on Apr. 17, 2013, abandoned.
Application 13/864,245 is a continuation of application No. 13/803,437, filed on Mar. 14, 2013, granted, now 9,385,058, issued on Jul. 5, 2016.
Application 13/803,437 is a continuation in part of application No. 13/731,108, filed on Dec. 30, 2012, granted, now 9,871,034, issued on Jan. 16, 2018.
Application 13/731,108 is a continuation of application No. 13/730,897, filed on Dec. 29, 2012, abandoned.
Prior Publication US 2019/0006192 A1, Jan. 3, 2019
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/098 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 27/02 (2006.01); H01L 21/8234 (2006.01); H01L 27/06 (2006.01); H01L 25/065 (2006.01); H01L 27/092 (2006.01); H01L 23/60 (2006.01); H01L 23/522 (2006.01); H01L 23/367 (2006.01); H01L 25/00 (2006.01); H01L 27/088 (2006.01); H01L 23/34 (2006.01); H01L 23/373 (2006.01); H01L 27/108 (2006.01)
CPC H01L 21/4871 (2013.01) [H01L 21/823487 (2013.01); H01L 23/367 (2013.01); H01L 23/3677 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/5226 (2013.01); H01L 23/60 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 27/0207 (2013.01); H01L 27/0688 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 27/098 (2013.01); H01L 23/34 (2013.01); H01L 23/373 (2013.01); H01L 23/3732 (2013.01); H01L 27/0248 (2013.01); H01L 27/0922 (2013.01); H01L 27/108 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/00 (2013.01); H01L 2924/0002 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A multi-level semiconductor device, the device comprising:
a first level comprising a plurality of single crystal first transistors;
a second level comprising a plurality of second transistors,
wherein said first level is overlaid by said second level;
a third level comprising a plurality of single crystal third transistors,
wherein said second level is overlaid by said third level,
wherein said device comprises Input/Output (“1/0”) circuits for connecting said device to an external device,
wherein at least one of said Input/Output circuits comprises at least one of said third transistors,
wherein at least one of said Input/Output circuits is connected to at least one of said first transistors; and
a plurality of vias providing connections between said first transistors and said second transistors,
wherein said plurality of vias each have a diameter of less than 400 nm and greater than 5 nm wherein said third level comprises a first power distribution grid, wherein said first level comprises a second power distribution grid, wherein said first power distribution grid connectivity is at least double that of said second power distribution grid connectivity.