US 10,892,101 B2
Multilayer ceramic capacitor
Jin Woo Lee, Suwon-Si (KR); Hyun Hee Gu, Suwon-Si (KR); Eui Hyun Jo, Suwon-Si (KR); Jong Ho Lee, Suwon-Si (KR); Eun Jin Kim, Suwon-si (KR); and Hye Young Choi, Suwon-Si (KR)
Assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRO-MECHANICS CO., LTD., Suwon-Si (KR)
Filed on Nov. 8, 2018, as Appl. No. 16/184,674.
Claims priority of application No. 10-2018-0106589 (KR), filed on Sep. 6, 2018.
Prior Publication US 2020/0082987 A1, Mar. 12, 2020
Int. Cl. H01G 4/232 (2006.01); H01G 4/248 (2006.01); H01G 4/30 (2006.01); H01G 4/12 (2006.01); H01G 4/005 (2006.01); H01G 4/228 (2006.01)
CPC H01G 4/30 (2013.01) [H01G 4/005 (2013.01); H01G 4/1227 (2013.01); H01G 4/228 (2013.01); H01G 4/232 (2013.01); H01G 4/248 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A multilayer ceramic capacitor, comprising:
a body including a dielectric layer and an internal electrode; and
an external electrode disposed on the body,
wherein the external electrode comprises an electrode layer connected to the internal electrode, a first plating portion disposed on the electrode layer and having a thickness ranging from 0.3 μm to 1 μm, and a second plating portion disposed on the first plating portion,
the first plating portion comprises an Sn plated layer, and the second plating portion comprises an Ni plated layer and an Sn plated layer sequentially disposed on the first plating portion,
the first plating portion and the second plating portion have an Sn—Ni intermetallic compound layer disposed at an interfacial area therebetween, and
the Sn—Ni intermetallic compound layer has an outer surface substantially covered by the Sn plated layer of the second plating portion.