US 10,892,028 B2
Shift register and method of driving the same, gate driving circuit and display device
Yuanbo Zhang, Beijing (CN); Xiaolin Wang, Beijing (CN); Zhuo Xu, Beijing (CN); Shuai Chen, Beijing (CN); and Zhulin Liu, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN); and Chongqing BOE Optoelectronics Technology Co., Ltd., Chongqing (CN)
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN); and CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Chongqing (CN)
Filed on Aug. 20, 2018, as Appl. No. 16/105,274.
Claims priority of application No. 2018 1 0006247 (CN), filed on Jan. 3, 2018.
Prior Publication US 2019/0206503 A1, Jul. 4, 2019
Int. Cl. G11C 19/00 (2006.01); G11C 19/28 (2006.01); G09G 3/20 (2006.01); G09G 3/36 (2006.01)
CPC G11C 19/287 (2013.01) [G09G 3/20 (2013.01); G09G 3/3677 (2013.01); G11C 19/28 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A gate driving circuit, comprising a plurality of shift registers connected in cascade, wherein each of the plurality of shift registers comprises
a pull-up control circuit connected to a signal input terminal and a pull-up node, wherein the pull-up control circuit is configured to pull up a potential of the pull-up node to a potential of a signal from the signal input terminal under a control of the signal from the signal input terminal;
a pull-up circuit connected to the pull-up node, a clock signal terminal and a signal output terminal, wherein the pull-up circuit is configured to output a signal from the clock signal terminal to the signal output terminal under a control of the pull-up node;
a pull-down control circuit connected to a first control terminal, a pull-down node, a first voltage terminal, and the pull-up node, wherein the pull-down control circuit is configured to pull down a potential of the pull-down node to a potential of the first voltage terminal under the control of the pull-up node, and to output a signal from the first control terminal to the pull-down node under a control of the signal from the first control terminal;
a pull-down circuit connected to the pull-down node, the pull-up node, a second control terminal, the first voltage terminal, and the signal output terminal, wherein the pull-down circuit is configured to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under a control of the pull-down node, and to pull down potentials of the pull-up node and the signal output terminal to a potential of the first voltage terminal under a control of a signal from the second control terminal; and
a reset circuit connected to a reset signal terminal, the first voltage terminal, and the pull-up node, wherein the reset circuit is configured to pull down a potential of the pull-up node to a potential of the first voltage terminal under a control of a signal from the reset signal terminal; wherein,
a signal input terminal of a first-stage shift register is connected to a start signal terminal; except for the first-stage shift register, a signal input terminal of each of remaining stages of shift registers is connected to a signal output terminal of a shift register in a previous stage;
except for a last-stage shift register, a reset signal terminal of each of remaining stages of shift registers is connected to a signal output terminal of a shift register in a next stage; a reset signal terminal of the last-stage shift register is connected to the start signal terminal;
adjacent stages of shift registers constitute a shift register group, and the gate driving circuit comprises M+1 shift register groups;
the gate driving circuit is connected to M+1 first control signal input terminals, wherein first control terminals of shift registers in different shift register groups are connected to different first control signal input terminals, and first control terminals of shift registers in the same shift register group are connected to a same first control signal input terminal;
the gate driving circuit is connected to M+1 second control signal input terminals, wherein each stage of shift registers is connected to M second control signal input terminals; each stage of shift registers in a same shift register group is connected to same M second control signal input terminals, and a second control signal input terminal that is not connected in different shift register groups is different;
a switching frequency of a high level and a low level of the first control terminal and the second control terminal in one frame of image is less than the switching frequency of the high level and the low level of the clock signal terminal in one frame of image;
the first control terminal and the second control terminal are non-clock signal terminals outside the gate driving circuit; and
M is an integer and M≥1.