US 10,892,026 B2
Memory management method, memory storage device and memory control circuit unit
Wei Lin, Taipei (TW); An-Cheng Liu, Taipei (TW); Szu-Wei Chen, New Taipei (TW); and Yu-Siang Yang, New Taipei (TW)
Assigned to PHISON ELECTRONICS CORP., Miaoli (TW)
Filed by PHISON ELECTRONICS CORP., Miaoli (TW)
Filed on Jun. 8, 2018, as Appl. No. 16/3,114.
Claims priority of application No. 107112940 A (TW), filed on Apr. 16, 2018.
Prior Publication US 2019/0318791 A1, Oct. 17, 2019
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/349 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A memory management method for a memory storage device comprising a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of memory cells, and the memory management method comprises:
randomizing original data to generate first data, wherein the original data is from a host system and comprises data to be stored;
programming the first data into a plurality of first memory cells among the memory cells, such that the programmed first memory cells have a plurality of states, wherein each of the plurality of states corresponds to a default bit value;
sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level;
obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence;
sending a second single-stage read command sequence which indicates to read the programmed first memory cells by using a plurality of second read voltage levels according to the first count information, wherein a plurality of voltage ranges are classified by the second read voltage levels;
obtaining second count information reflecting a number of at least one memory cell each having a voltage level belonging to one of the voltage ranges according to a reading result corresponding to the second single-stage read command sequence; and
adjusting the first read voltage level according to the first count information, the second count information and default count information corresponding to the first read voltage level.