US 10,892,017 B2
Memory device and a storage system using the same
Sang Wan Nam, Hwaseong-si (KR); Yong Hyuk Choi, Suwon-si (KR); Jun Yong Park, Seoul (KR); and Jung No Im, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jul. 10, 2019, as Appl. No. 16/508,016.
Claims priority of application No. 10-2018-0116555 (KR), filed on Sep. 28, 2018.
Prior Publication US 2020/0105347 A1, Apr. 2, 2020
Int. Cl. G11C 11/34 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 7/10 (2006.01); G11C 16/04 (2006.01); G06F 12/02 (2006.01)
CPC G11C 16/14 (2013.01) [G11C 7/1006 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G06F 12/02 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first memory cell, and a second memory cell different from the first memory cell and disposed above or below the first memory cell, wherein the first memory cell and the second memory cell are included in a same memory block as each other;
a first word line connected to the first memory cell;
a second word line, different from the first word line, connected to the second memory cell;
an address decoder which is configured to apply one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and
a control logic which is configured to control an erasing operation on the memory block, using the address decoder,
wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied, and
wherein the erase voltage is applied to the first word line for a first time period, and the erase voltage is applied to the second word line for a second time period which is longer than or shorter than the first time period.