US 10,892,008 B2
Multi word line assertion
Hidehiro Fujiwara, Hsinchu (TW); Hsien-Yu Pan, Hsinchu (TW); Chih-Yu Lin, Hsinchu (TW); Yen-Huei Chen, Hsinchu (TW); and Wei-Chang Zhao, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 7, 2019, as Appl. No. 16/434,746.
Claims priority of provisional application 62/685,547, filed on Jun. 15, 2018.
Prior Publication US 2019/0385671 A1, Dec. 19, 2019
Int. Cl. G11C 11/418 (2006.01)
CPC G11C 11/418 (2013.01) 19 Claims
OG exemplary drawing
1. An apparatus comprising:
a first segment comprising a first plurality of memory cells;
a second segment comprising a second plurality of memory cells wherein the first segment is positioned over the second segment;
a first Bit Line (BL) corresponding to the first segment wherein the first BL goes over the second segment in a flying BL scheme;
a first Word Line (WL) corresponding to the first segment; and
a second WL corresponding to the second segment wherein the first WL and the second WL are configured to be activated in one cycle.