US 10,891,997 B2
Memory array with horizontal source line and a virtual source line
Neal Berger, Cupertino, CA (US); Mourad El Baraji, Fremont, CA (US); Lester Crudele, Tomball, TX (US); and Benjamin Louie, Fremont, CA (US)
Assigned to Spin Memory, Inc., Fremont, CA (US)
Filed by SPIN MEMORY, Inc., Fremont, CA (US)
Filed on Dec. 28, 2017, as Appl. No. 15/857,241.
Prior Publication US 2019/0206471 A1, Jul. 4, 2019
Int. Cl. G11C 11/16 (2006.01)
CPC G11C 11/1675 (2013.01) [G11C 11/1655 (2013.01); G11C 11/1659 (2013.01); G11C 11/1697 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device comprising:
an array of memory cells wherein each memory cell comprises:
a respective magnetic random access memory (MRAM) element; and
a respective gating transistor;
a plurality of bit lines which are routed parallel to each other, wherein each bit line is associated with respective memory cells of said array of memory cells;
a common word line coupled to gates of gating transistors of said array of memory cells;
a common source line coupled to sources of said gating transistors, wherein said common source line is routed perpendicular to said plurality of bit lines within said array of memory cells, wherein said common source line biased at a medium voltage;
a first circuit for providing a first voltage on an addressed bit line of said plurality of bit lines during a write cycle, wherein said addressed bit line corresponds to an addressed memory cell, and wherein said first voltage comprises a voltage between 0V and a high voltage; and
a second circuit for providing a second voltage on remainder bit lines of unselected memory cells on said common word line, wherein said second voltage is operable to be applied to said common source line through said unselected memory cells, wherein said write cycle stores a logical one into said addressed memory cell when said common bit line is driven to 0V and said source line is driven to the medium voltage, wherein said write cycle stores a logical zero intro said addressed memory cell when said common bit line is driven to a voltage equal to a sum of the medium voltage and the high voltage, and wherein the high voltage is higher than said medium voltage.