US 10,891,973 B2
High-bandwidth STO bias architecture with integrated slider voltage potential control
John Contreras, Palo Alto, CA (US); Yunfei Ding, Fremont, CA (US); Kuok San Ho, Redwood City, CA (US); Ian Robson McFadyen, San Jose, CA (US); and Joey Martin Poss, Rochester, MN (US)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Mar. 11, 2020, as Appl. No. 16/816,211.
Application 16/816,211 is a continuation of application No. 16/537,594, filed on Aug. 11, 2019, granted, now 10,629,229.
Application 16/537,594 is a continuation of application No. 15/918,060, filed on Mar. 12, 2018, granted, now 10,424,323, issued on Sep. 24, 2019.
Application 15/918,060 is a continuation of application No. 15/395,157, filed on Dec. 30, 2016, abandoned.
Prior Publication US 2020/0211584 A1, Jul. 2, 2020
Int. Cl. G11B 5/02 (2006.01); G11B 5/09 (2006.01)
CPC G11B 5/02 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus for electrically biasing a spin-torque oscillator (STO), the apparatus comprising:
means for determining an amplitude of a high-frequency component of a bias current;
means for determining an amplitude of a low-frequency component of the bias current;
means for generating the high-frequency component based at least in part on the determined amplitude of the high-frequency component;
means for generating the low-frequency component based at least in part on the determined amplitude of the low-frequency component;
means for providing the high-frequency component to the STO; and
means for providing the low-frequency component to the STO.