US 10,891,913 B2
Shift register circuitry, gate driving circuit, and display device
Honggang Gu, Beijing (CN); Junsheng Chen, Beijing (CN); Xianjie Shao, Beijing (CN); Jie Song, Beijing (CN); and Lili Yao, Beijing (CN)
Assigned to BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN); and HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Hefei (CN)
Appl. No. 15/773,013
Filed by BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN); and HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Hefei (CN)
PCT Filed Nov. 17, 2017, PCT No. PCT/CN2017/111559
§ 371(c)(1), (2) Date May 2, 2018,
PCT Pub. No. WO2018/218886, PCT Pub. Date Jun. 12, 2018.
Claims priority of application No. 2017 1 0390668 (CN), filed on May 27, 2017.
Prior Publication US 2020/0243034 A1, Jul. 30, 2020
Int. Cl. G09G 3/36 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/3677 (2013.01) [G09G 3/3696 (2013.01); G11C 19/28 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A shift register circuitry comprising: a first shift register unit, a second shift register unit, a pull-down control sub-circuit, and a pull-down sub-circuit; wherein the first shift register unit comprises: a first input sub-circuit, a first output sub-circuit, a first reset sub-circuit, and a first noise reduction sub-circuit; the second shift register unit includes: a second input sub-circuit, a second output sub-circuit, a second reset sub-circuit, and a second noise reduction sub-circuit;
wherein the first input sub-circuit is configured to pre-charge a first pull-up node under control of a first input signal; the first pull-up node is a connection node between the first input sub-circuit, the first output sub-circuit, the pull-down sub-circuit, the first reset sub-circuit, and the first noise reduction sub-circuit;
the first output sub-circuit is configured to output a first clock signal through a first signal output terminal under control of a potential of the first pull-up node;
the first reset sub-circuit is configured to reset potentials of the first pull-up node and the first signal output terminal through a first voltage signal under control of a first reset signal;
the second input sub-circuit is configured to pre-charge a second pull-up node under control of a second input signal; the second pull-up node is a connection node between the second input sub-circuit, the second output sub-circuit and the pull-down sub-circuit;
the second output sub-circuit is configured to output a second clock signal through a second signal output terminal under control of a potential of the second pull-up node;
the second reset sub-circuit is configured to reset potentials of the second pull-up node and the second signal output terminal through the first voltage signal under control of a second reset signal;
the pull-down control sub-circuit is configured to control a potential of a pull-down node under control of the first clock signal or the second clock signal; the pull-down node is a connection node between the pull-down control sub-circuit, the pull-down sub-circuit, the first noise reduction sub-circuit and the second noise reduction sub-circuit;
the pull-down sub-circuit is configured to pull down a potential of the pull-down node through the first voltage signal under control of a potential of the first pull-up node and a potential of the second pull-up node;
the first noise reduction sub-circuit is configured to reduce output noise of the first pull-up node and the first signal output terminal through the first voltage signal under control of the pull-down node; and
the second noise reduction sub-circuit is configured to reduce output noise of the second pull-up node and the second signal output terminal through the first voltage signal under control of the pull-down node,
wherein the pull-down sub-circuit comprises a ninth transistor, a tenth transistor, and a twelfth transistor,
wherein a first electrode and a control electrode of the ninth transistor are both connected to the first pull-up node and a second electrode of the ninth transistor is connected to a control electrode of the twelfth transistor;
a first electrode and a control electrode of the tenth transistor are both connected to the second pull-up node, and a second electrode of the tenth transistor is connected to the control electrode of the twelfth transistor, and
a first electrode of the twelfth transistor is connected to the pull-down node, a second electrode of the twelfth transistor is connected to a first voltage signal terminal, and the control electrode of the twelfth transistor is connected to the second electrode of a first transistor and the second electrode of the tenth transistor.