US 10,891,884 B1
Test-response comparison circuit and scan data transfer scheme in a DFT architecture for micro LED based display panels
Bo Yang, Santa Clara, CA (US); Xiang Lu, Campbell, CA (US); Andrew J. Copperhall, Redwood City, CA (US); Henry C. Jen, Los Altos, CA (US); Karthik Manickam, Santa Clara, CA (US); Sagar Nataraj, San Jose, CA (US); Shriram Vijayakumar, Santa Clara, CA (US); and Derek K. Shaeffer, Redwood City, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 21, 2019, as Appl. No. 16/281,996.
Claims priority of provisional application 62/684,911, filed on Jun. 14, 2018.
Int. Cl. G09G 3/00 (2006.01); G09G 3/32 (2016.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01); G01R 31/58 (2020.01)
CPC G09G 3/006 (2013.01) [G01R 31/31704 (2013.01); G01R 31/318583 (2013.01); G01R 31/58 (2020.01); G09G 3/32 (2013.01); G09G 2310/0283 (2013.01); G09G 2330/12 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A comparison circuit comprising:
plurality of scan-data out (SDO) inputs;
a corresponding plurality of comparators to compare SDO data streams from the plurality of SDO inputs with an expected data stream, each comparator to transmit a compared data stream indicative of whether or not an error exists in the any of the SDO data streams;
a corresponding plurality of sticky registers coupled to the plurality of comparators, each sticky register to store a value indicative if an error is present in the compared data stream; and
a scan-chain register to store values from the corresponding plurality of sticky registers.