US 10,891,773 B2
Apparatus and method for efficient graphics virtualization
Joydeep Ray, Folsom, CA (US); Abhishek R. Appu, El Dorado Hills, CA (US); Pattabhiraman K, Bangalore (IN); Balaji Vembu, Folsom, CA (US); Altug Koker, El Dorado Hills, CA (US); Niranjan L. Cooray, Folsom, CA (US); and Josh B. Mastronarde, Sacramento, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 7, 2017, as Appl. No. 15/482,677.
Prior Publication US 2018/0293776 A1, Oct. 11, 2018
Int. Cl. G06T 15/00 (2011.01); G06F 9/455 (2018.01); G06T 1/60 (2006.01); G09G 5/36 (2006.01); G09G 5/00 (2006.01); G09G 5/393 (2006.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06T 15/04 (2011.01); G06T 15/80 (2011.01); G06T 17/10 (2006.01); G06T 17/20 (2006.01)
CPC G06T 15/005 (2013.01) [G06F 9/45504 (2013.01); G06F 9/45558 (2013.01); G06F 9/4806 (2013.01); G06F 9/5011 (2013.01); G06T 1/60 (2013.01); G09G 5/001 (2013.01); G09G 5/363 (2013.01); G09G 5/393 (2013.01); G06F 9/5016 (2013.01); G06F 9/5044 (2013.01); G06F 2009/45583 (2013.01); G06T 15/04 (2013.01); G06T 15/80 (2013.01); G06T 17/10 (2013.01); G06T 17/20 (2013.01); G09G 2360/08 (2013.01); G09G 2360/10 (2013.01); G09G 2360/121 (2013.01); G09G 2360/122 (2013.01); G09G 2360/125 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A processor comprising:
a command streamer to queue commands from a plurality of virtual machines (VMs), the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU);
a tile cache to store graphics data associated with the plurality of VMs as the commands are executed by the graphics processing resources; and
tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM and a second portion of the tile cache to a second VM, wherein a priority associated with each of the plurality of VMs and sizes of the first portion and second portion of the tile cache are selected in accordance with the priorities;
the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data for the first VM when the first portion of the tile cache allocated to the first VM becomes full and the second portion of the tile cache allocated to the second VM is available.