US 10,891,396 B2
Electronic circuit performing encryption/decryption operation to prevent side- channel analysis attack, and electronic device including the same
Hong-Mook Choi, Bucheon-si (KR); Yun-Ho Youm, Seoul (KR); Sang-Hyun Park, Seoul (KR); and Hyesoo Lee, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 17, 2017, as Appl. No. 15/488,639.
Claims priority of application No. 10-2016-0065955 (KR), filed on May 27, 2016; and application No. 10-2016-0098292 (KR), filed on Aug. 2, 2016.
Prior Publication US 2017/0344759 A1, Nov. 30, 2017
Int. Cl. G06F 21/00 (2013.01); H04L 29/06 (2006.01); G06F 21/72 (2013.01); H04L 9/00 (2006.01); G09C 1/00 (2006.01); G06F 1/06 (2006.01)
CPC G06F 21/72 (2013.01) [G06F 1/06 (2013.01); G09C 1/00 (2013.01); H04L 9/003 (2013.01); H04L 2209/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic circuit comprising:
an operator comprising a logic circuit configured to receive an activation signal and perform encryption and/or decryption of input data, the logic circuit comprising a plurality of logic gates; and
a controller configured to generate the activation signal, based on a control signal and a clock signal, to control the operator,
wherein, if the activation signal has a first value, each of the plurality of logic gates outputs a first logic value, and
if the activation signal has a second value which is different from the first value, the plurality of logic gates generate outputs depending on the input data, and
for cycles of the activation signal having the second value, the number of the plurality of logic gates each of which outputs the first logic value and the number of the plurality of logic gates each of which outputs a second logic value are constant, such that an amount of power that is consumed by the logic circuit is constant in each of the cycles of the activation signal having the second value.