US 10,891,353 B2
Apparatus and methods for matrix addition and subtraction
Xiao Zhang, Beijing (CN); Shaoli Liu, Beijing (CN); Tianshi Chen, Beijing (CN); and Yunji Chen, Beijing (CN)
Assigned to CAMBRICON TECHNOLOGIES CORPORATION LIMITED, Beijing (CN)
Filed by Cambricon Technologies Corporation Limited, Beijing (CN)
Filed on Jan. 17, 2019, as Appl. No. 16/250,123.
Application 16/250,123 is a continuation of application No. 16/171,681, filed on Oct. 26, 2018, abandoned.
Application 16/171,681 is a continuation in part of application No. PCT/CN2016/081117, filed on May 5, 2016.
Claims priority of application No. 2016 1 0266805 (CN), filed on Apr. 26, 2016.
Prior Publication US 2019/0147015 A1, May 16, 2019
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 17/16 (2006.01); G06N 3/04 (2006.01)
CPC G06F 17/16 (2013.01) [G06N 3/04 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus for matrix operations in a neural network, comprising:
a controller circuit configured to receive a matrix-addition instruction that indicates a first address of a first matrix, a second address of a second matrix, a first size of the first matrix, a second size of the second matrix, and an output address;
a matrix operation circuit configured to:
retrieve the first matrix and the second matrix from a storage device based on the first address of the first matrix and the second address of the second matrix,
wherein the first matrix includes one or more first elements and the second matrix includes one or more second elements, and
wherein the one or more first elements and the one or more second elements are arranged in accordance with a two-dimensional data structure, and
respectively add each of the first elements to each of the second elements based on a correspondence in the two-dimensional data structure in accordance with the matrix-addition instruction to generate one or more third elements for a third matrix, wherein the matrix operation circuit includes multiple adders configured to parallelly add elements in a first portion of the first elements to elements in a second portion of the second elements to generate a partial result vector of the third matrix; and
an instruction register configured to store the first address of the first matrix, the first size of the first matrix, the second address of the second matrix, the second size of the second matrix, and the output address.